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HN29W6484AH03TE-1 controller for and flash memory ade-203-988a (z) rev. 1.0 apr. 16, 1999 description HN29W6484AH03TE-1 is a controller ic for flash ata card. this ic is manufactured based on hitachi 0.5 m cmos technology, and integrates control logic with 8 bit micro processor. this ic is able to control maximum 20 pieces of hitachi 64 mega bit flash memory hn29w6411a and maximum 2 pieces of hitachi 84 mega bit flash memory hn29w8411, and is used to build flash ata card and compactflash tm . features comform to pc-ata card and compactflash tm specification standard control maximum 20 pieces of hitachi 64 mega bit flash memory hn29w6411a and maximum 2 pieces of hitachi 84 mega bit flash memory hn29w8411 operate by 3.3v or 5v single power supply support card density up to 160/20 mega bytes execute internal self-diagnostic program at v cc power on operate in 3 modes ? memory card mode ? i/o card mode ? true-ide mode assure a high reliability based on the internal ecc (error correcting code) function support auto sleep mode support interleave operation in 2 bank organization note: compactflash tm is a trademark of sandisk corporation and is licensed royalty-free to the cfa which in turn will license it royalty-free to cfa members. *cfa: compactflash tm association.
HN29W6484AH03TE-1 2 pin assignment memory card mode i/o card mode true ide mode no. controller signal name i/o signal name i/o signal name i/o remarks* 1 1 h_a(2) a2 i a2 i a2 i pc3b43c 2 h_inpack_ Cinpack o Cinpack o Cinpack o pc3bi3c 3 h_reg_ Creg i Creg i Creg i pc3b63vc 4 dasp_ bvd2 i/o Cspkr i/o Cdasp i/o pc3b43vc 5 h_stschg_ bvd1 i/o Cstschg i/o Cpdiag i/o pc3b43vc 6 h_a(1) a1 i a1 i a1 i pc3b43c 7 h_a(0) a0 i a0 i a0 i pc3b43c 8 gnd gnd gnd gnd pv0a 9 h_d(0) d0 i/o d0 i/o d0 i/o pc3bh3cx 10 h_d(1) d1 i/o d1 i/o d1 i/o pc3bh3cx 11 h_d(2) d2 i/o d2 i/o d2 i/o pc3bh3cx 12 h_iois16_ wp o Ciois16 o Ciois16 o pc3n03c 13 h_d(8) d8 i/o d8 i/o d8 i/o pc3bh3cx 14 h_d(9) d9 i/o d9 i/o d9 i/o pc3bh3cx 15 h_d(10) d10 i/o d10 i/o d10 i/o pc3bh3cx 16 vcc vcc vcc vcc pv3i 17 test4 o o o pc3bi3c 18 porst_ porst_ i porst_ i porst_ i pc3b63c 19 test1 i i i pc3b63c 20 test2 i i i pc3d21 21 gnd gnd gnd gnd pv0i 22 xin xin i xin i xin i pc3x11h 23 xout xout o xout o xout o pc3x11oh 24 gnd gnd gnd gnd pv0a 25 vcc vcc vcc vcc pv3a 26 f_web_ f_web_ o f_web_ o f_web_ o pc3b43c 27 f_sc_b1 f_sc_b1 o f_sc_b1 o f_sc_b1 o pc3b43c 28 f_sc_b2 f_sc_b2 o f_sc_b2 o f_sc_b2 o pc3b43c 29 f_db(7) f_db(7) i/o f_db(7) i/o f_db(7) i/o pc3b42ux 30 f_db(6) f_db(6) i/o f_db(6) i/o f_db(6) i/o pc3b42ux
HN29W6484AH03TE-1 3 pin assignment (cont.) memory card mode i/o card mode true ide mode no. controller signal name i/o signal name i/o signal name i/o remarks* 1 31 f_db(5) f_db(5) i/o f_db(5) i/o f_db(5) i/o pc3b42ux 32 f_db(4) f_db(4) i/o f_db(4) i/o f_db(4) i/o pc3b42ux 33 f_db(3) f_db(3) i/o f_db(3) i/o f_db(3) i/o pc3b42ux 34 gnd gnd gnd gnd pv0a 35 f_db(2) f_db(2) i/o f_db(2) i/o f_db(2) i/o pc3b42ux 36 f_db(1) f_db(1) i/o f_db(1) i/o f_db(1) i/o pc3b42ux 37 f_db(0) f_db(0) i/o f_db(0) i/o f_db(0) i/o pc3b42ux 38 f_oeb_ f_oeb_ o f_oeb_ o f_oeb_ o pc3b42c 39 f_cdeb_ f_cdeb_ o f_cdeb_ o f_cdeb_ o pc3b42c 40 f_rdy_2 f_rdy_2 i f_rdy_2 i f_rdy_2 i pc3b63uc 41 f_res_ f_res_ o f_res_ o f_res_ o pc3o03c 42 f_ceb_1 f_ceb_1 o f_ceb_1 o f_ceb_1 o pc3b43c 43 f_ceb_2 f_ceb_2 o f_ceb_2 o f_ceb_2 o pc3b43c 44 f_ceb_3 f_ceb_3 o f_ceb_3 o f_ceb_3 o pc3b43c 45 test3 i i i @ 46 vcc vcc vcc vcc pv3i 47 test5 i/o i/o i/o pc3b63uc 48 gnd gnd gnd gnd pv0a 49 f_ceb_4 f_ceb_4 o f_ceb_4 o f_ceb_4 o pc3b43c 50 f_ceb_5 f_ceb_5 o f_ceb_5 o f_ceb_5 o pc3b43c 51 gnd gnd gnd gnd pv0i 52 f_ceb_6 f_ceb_6 o f_ceb_6 o f_ceb_6 o pc3b43c 53 f_ceb_7 f_ceb_7 o f_ceb_7 o f_ceb_7 o pc3b43c 54 f_ceb_8 f_ceb_8 o f_ceb_8 o f_ceb_8 o pc3b43c 55 f_ceb_9 f_ceb_9 o f_ceb_9 o f_ceb_9 o pc3b43c 56 f_ceb_10 f_ceb_10 o f_ceb_10 o f_ceb_10 o pc3b43c 57 f_cea_1 f_cea_1 o f_cea_1 o f_cea_1 o pc3bh3uc 58 f_cea_2 f_cea_2 o f_cea_2 o f_cea_2 o pc3bh3uc 59 vcc vcc vcc vcc pv3a 60 f_sc_a1 f_sc_a1 o f_sc_a1 o f_sc_a1 o pc3b43c
HN29W6484AH03TE-1 4 pin assignment (cont.) memory card mode i/o card mode true ide mode no. controller signal name i/o signal name i/o signal name i/o remarks* 1 61 f_sc_a2 f_sc_a2 o f_sc_a2 o f_sc_a2 o pc3b43c 62 gnd gnd gnd gnd pv0a 63 f_cea_3 f_cea_3 o f_cea_3 o f_cea_3 o pc3bh3uc 64 f_cea_4 f_cea_4 o f_cea_4 o f_cea_4 o pc3bh3uc 65 f_cea_5 f_cea_5 o f_cea_5 o f_cea_5 o pc3bh3uc 66 f_cea_6 f_cea_6 o f_cea_6 o f_cea_6 o pc3bh3uc 67 f_cea_7 f_cea_7 o f_cea_7 o f_cea_7 o pc3bh3uc 68 f_cea_8 f_cea_8 o f_cea_8 o f_cea_8 o pc3bh3uc 69 gnd gnd gnd gnd pv0i 70 f_cea_9 f_cea_9 o f_cea_9 o f_cea_9 o pc3bh3uc 71 f_cea_10 f_cea_10 o f_cea_10 o f_cea_10 o pc3bh3uc 72 f_wea_ f_wea_ o f_wea_ o f_wea_ o pc3b43uc 73 f_da(7) f_da(7) i/o f_da(7) i/o f_da(7) i/o pc3b42ux 74 f_da(6) f_da(6) i/o f_da(6) i/o f_da(6) i/o pc3b42ux 75 f_da(5) f_da(5) i/o f_da(5) i/o f_da(5) i/o pc3b42ux 76 vcc vcc vcc vcc pv3a 77 f_da(4) f_da(4) i/o f_da(4) i/o f_da(4) i/o pc3b42ux 78 f_da(3) f_da(3) i/o f_da(3) i/o f_da(3) i/o pc3b42ux 79 f_da(2) f_da(2) i/o f_da(2) i/o f_da(2) i/o pc3b42ux 80 f_da(1) f_da(1) i/o f_da(1) i/o f_da(1) i/o pc3b42ux 81 gnd gnd gnd gnd pv0a 82 f_da(0) f_da(0) i/o f_da(0) i/o f_da(0) i/o pc3b42ux 83 f_oea_ f_oea_ i/o f_oea_ i/o f_oea_ i/o pc3b42uc 84 f_cdea_ f_cdea_ i/o f_cdea_ i/o f_cdea_ i/o pc3b42uc 85 f_rdy_1 f_rdy_1 i f_rdy_1 i f_rdy_1 i pc3b63uc 86 test6 o o o pc3bi3c 87 vcc vcc vcc vcc pv3i 88 gnd gnd gnd gnd pv0a 89 h_d(3) d3 i/o d3 i/o d3 i/o pc3bh3cx 90 h_d(4) d4 i/o d4 i/o d4 i/o pc3bh3cx
HN29W6484AH03TE-1 5 pin assignment (cont.) memory card mode i/o card mode true ide mode no. controller signal name i/o signal name i/o signal name i/o remarks* 1 91 h_d(5) d5 i/o d5 i/o d5 i/o pc3bh3cx 92 h_d(6) d6 i/o d6 i/o d6 i/o pc3bh3cx 93 h_d(11) d11 i/o d11 i/o d11 i/o pc3bh3cx 94 h_d(12) d12 i/o d12 i/o d12 i/o pc3bh3cx 95 h_d(13) d13 i/o d13 i/o d13 i/o pc3bh3cx 96 gnd gnd gnd gnd pv0a 97 h_d(14) d14 i/o d14 i/o d14 i/o pc3bh3cx 98 h_d(7) d7 i/o d7 i/o d7 i/o pc3bh3cx 99 h_ce1_ Cce1 i Cce1 i Cce1 i pc3b63vc 100 h_a(10) a10 i a10 i a10 i pc3b43c 101 h_oe_ Coe i Coe i Catasel i pc3b63c 102 h_d(15) d15 i/o d15 i d15 i pc3bh3cx 103 h_ce2_ Cce2 i Cce2 i Cce2 i pc3b63vc 104 h_iord_ Ciord i Ciord i Ciord i pc3b63vc 105 h_iowr_ Ciowr i Ciowr i Ciowr i pc3b63vc 106 vcc vcc vcc vcc pv3a 107 h_a(9) a9 i a9 i a9 i pc3b43c 108 h_a(8) a8 i a8 i a8 i pc3b43c 109 h_a(7) a7 i a7 i a7 i pc3b43c 110 h_a(6) a6 i a6 i a6 i pc3b43c 111 gnd gnd i gnd i gnd i pv0a 112 h_we_ Cwe i Cwe i Cwe i pc3b63vc 113 h_ireq_ rdy/Cbsy o Cireq o intrq o pc3bi3c 114 csel_ Ccsel i Ccsel i Ccsel i pt3b43vc 115 test7 o o o @ 116 h_reset reset i reset i Creset i pt3b43c 117 h_wait_ Cwait o Cwait o iordy o pc3bi3c 118 h_a(5) a5 i a5 i a5 i pc3b43c 119 h_a(4) a4 i a4 i a4 i pc3b43c 120 h_a(3) a3 i a3 i a3 i pc3b43c
HN29W6484AH03TE-1 6 note: 1. type of input/output buffer pc3b42c : cmos level 3-state input/output (2 ma) pc3b42uc : cmos level 3-state input/output with pull-up resister (2 ma) pc3b42ux : cmos level 3-state input/output with pull-up resister (1 ma/2 ma) pc3b43c : cmos level 3-state input/output (3 ma) pc3b43uc : cmos level 3-state input/output with pull-up resister (3 ma) pc3b43vc : cmos level 3-state input/output with pull-up resister 100 k w (3 ma) pc3b63c : cmos level 3-state input/output with schmitt input (3 ma) pc3b63uc : cmos level 3-state input/output with schmitt input, pull-up resister (3 ma) pc3b63vc : cmos level 3-state input/output with schmitt input, pull-up resister 100 k w (3 ma) pc3bh3cx : cmos level 3-state input/output with active-low input enable (2 ma/3 ma) pc3bh3uc : cmos level 3-state input/output with active-low input enable and pull-up resister (3 ma) pc3bi3c : cmos level 3-state input/output with 3-state input enable (3 ma) pc3d21 : cmos level schmitt input only pc3n03c : open drain output (3 ma) pc3o03c : topempole output (3 ma) pc3x11h : crystal osc input pc3x11oh : crystal osc output pt3b43c : ttl level input/output (3 ma) pt3b43vc : ttl level input/output with pull-up resister 100 k w (3 ma) pv0a : i/o gnd pv0i : core and i/o gnd pv3a : i/o vcc pv3i : core and i/o vcc @ : test pin only
HN29W6484AH03TE-1 7 host interface pin explanation signal name direction pin no. description a10 to a0 (pc card memory mode) i 100, 107, 108, 109, 110, 118, 119, 120, 1, 6, 7 address bus is a10 to a0. a10 is msb and a0 is lsb. a10 to a0 (pc card i/o mode) a2 to a0 (true ide mode) 1, 6, 7 address bus is a10 to a0. only a2 to a0 are used, the remaining address lines should be grounded by the host. bvd1 (pc card memory mode) i/o 5 bvd1 outputs the battery voltage status in the card. this output line is constantly driven to a high state since a battery is not required for this product. -stschg (pc card i/o mode) -stschg is used for changing the status of configuration and status register in attribute area. -pdiag (true ide mode) -pdiag is the pass diagnostic signal in master/slave handshake protocol. bvd2 (pc card memory mode) i/o 4 bvd2 outputs the battery voltage status in the card. this output line is constantly driven to a high state since a battery is not required for this product. -spkr (pc card i/o mode) -spkr outputs speaker signals. this output line is constantly driven to a high state since this product does not support the audio function. -dasp (true ide mode) -dasp is the disk active/slave present signal in the master/slave handshake protocol. -ce1, -ce2 (pc card memory mode) card enable i 99, 103 -ce1 and -ce2 are low active card select signals. byte/word/odd byte mode are defined by combination of -ce1, -ce2 and a0. -ce1, -ce2 (pc card i/o mode) card enable -ce1, -ce2 (true ide mode) -ce2 is used for select the alternate status register and the device control register while -ce1 is the chip select for the other task file registers.
HN29W6484AH03TE-1 8 signal name direction pin no. description -csel (pc card memory mode) i 114 this signal is not used. -csel (pc card i/o mode) -csel (true ide mode) this signal is used to configure this device as a master or a slave when configured in the true ide mode. when this pin is grounded, this device is configured as a master. when the pin is open, this device is configured as a slave. d15 to d0 (pc card memory mode) i/o 102, 97, 95, 94, 93, 15, 14, 13, 98, 92, 91, 90, 89, 11, 10, 9 data bus is d15 to d0. d0 is the lsb of the even byte of the word. d8 is the lsb of the odd byte of the word. d15 to d0 (pc card i/o mode) d15 to d0 (true ide mode) gnd (pc card memory mode) 8, 21, 24, 34, 48, 51, 62, 69, 81, 88, 96, 111 ground gnd (pc card i/o mode) gnd (true ide mode) -inpack (pc card memory mode) o 2 this signal is not used and should not be connected at the host. -inpack (pc card i/o mode) input acknowledge this signal is asserted low by this card when the card is selected and responding to an i/o read cycle at the address that is on the address bus during -ce and -iord are low. this signal is used for the input data buffer control. -inpack (true ide mode) this signal is not used and should not be connected at the host. -iord (pc card memory mode) i 104 this signal is not used. -iord (pc card i/o mode) -iord is used for control of read data in i/o task file area. this card does not respond to -iord until i/o card interface setting up. -iord (true ide mode) -iord is used for control of read data in i/o task file area. this card does not respond to -iord until true ide interface setting up.
HN29W6484AH03TE-1 9 signal name direction pin no. description -iowr (pc card memory mode) i 105 this signal is not used. -iowr (pc card i/o mode) -iowr is used for control of data write in i/o task file area. this card does not respond to -iowr until i/o card interface setting up. -iowr (true ide mode) -iowr is used for control of data write in i/o task file area. this card does not respond to -iowr until true ide interface setting up. -oe (pc card memory mode) i 101 - oe is used for the control of reading registers data in attribute area or task file area. -oe (pc card i/o mode) - oe is used for the control of reading registers data in attribute area. -atasel (true ide mode) to enable true ide mode this input should be grounded by the host. rdy/-bsy (pc card memory mode) o 113 the signal is rdy/-bsy pin. rdy/-bsy pin turns low level during the card internal initialization operation at vcc applied or reset applied, so next access to the card should be after the signal turned high level. -ireq (pc card i/o mode) this signal is active low -ireq pin. the signal of low level indicates that the card is requesting software service to host, and high level indicates that the card is not requesting. intrq (true ide mode) this signal is the active high interrupt request to the host. -reg (pc card memory mode) attribute memory select i 3 -reg is used during memory cycles to disti nguish between task file and attribute memory accesses. high for task file, low for attribute memory is accessed. -reg (pc card i/o mode) -reg is constantly low when task file or attribute memory is accessed. -reg (true ide mode) this input signal is not used and should be connected to vcc.
HN29W6484AH03TE-1 10 signal name direction pin no. description reset (pc card memory mode) i 116 this signal is active high reset pin. if this signal is asserted high, the card internal initialization begins to operate. during the card internal initialization rdy/-bsy is low. after the card internal initialization rdy/-bsy is high. reset (pc card i/o mode) this signal is active high reset pin. if this signal is asserted high, the card internal initialization begins to operate. in this mode, rdy/-bsy signal can not be used, so using status register the ready/busy status can be confirmed. -reset (true ide mode) this signal is active low -reset pin. if this signal is asserted low, all the registers in this card are reset. in this mode, rdy/-bsy signal can not be used, so using status register the ready/busy status can be confirmed. vcc (pc card memory mode) 16, 25, 46, 59, 76, 87, 106 +5 v, +3.3 v power. vcc (pc card i/o mode) vcc (true ide mode) -wait (pc card memory mode) o 117 this signal is active low -wait pin. in this card this signal is constantly high level. -wait (pc card i/o mode) iordy (true ide mode) this output signal may be used as iordy. in this card this signal is constantly high impedance. -we (pc card memory mode) i 112 -we is used for the control of writing registers data in attribute memory area or task file area. -we (pc card i/o mode) -we is used for the control of writing registers data in attribute memory area. -we (true ide mode) this input signal is not used and should be connected to vcc by the host. wp (pc card memory mode) write protect o 12 wp is held low because this card does not have write protect switch. -iois16 (pc card i/o mode) -iois16 is asserted when task file registers are accessed in 16-bit mode. -iois16 (true ide mode) this output signal is asserted low when this device is expecting a word data transfer cycle. initial m ode is 16-bit. if the user issues a set feature command to put the device in byte access mode, the card permits 8-bit accesses.
HN29W6484AH03TE-1 11 flash memory interface pin explanation signal name direction pin no. description f_da7 to f_da0, f_db7 to f_db0 i/o 73, 74, 75, 77, 78, 79, 80, 82, 29, 30, 31, 32, 33, 35, 36, 37 the flash bus is f_da0 to f_da7 and f_db0 to f_db7. this bus is used as command, address and data bus for flash memory. f_cea10 to f_cea1, f_ceb10 to f_ceb1 o 71, 70, 68, 67, 66, 65, 64, 63, 58, 57, 56, 55, 54, 53, 52, 50, 49, 44, 43, 42 flash chip enable is used to select the flash memory. f_oea_, f_oeb_ o 83, 38 flash output enable is used to control read data output from the flash memory. f_rdy_1, f_rdy_2 i 85, 40 flash ready/busy is driven low by flash memory during program or erase operation. flash ready/busy becomes high impedance at the completion of the program or erase operation. f_wea_, f_web_ o 72, 26 flash write enable is used to strobe command and address. the command and address are latched at the rising edge of the flash write enable. f_sc_a1, f_sc_a2, f_sc_b1, f_sc_b2 o 60, 61, 27, 28 serial clock is used to read memory data and to strobe programming data. the programming data is latched at the rising edge of the serial clock. f_cdea_, f_cdeb_ o 84, 39 command data enable is used to control the multiplexed flash bus when flash write enable is asserted. command and data are latched when command data enable is low, and address is latched when command data enable is high. f_res_ o 41 flash reset must be kept at v ilr (vss 0.2v) while vcc is turned on and off to prevent flash memory from unintentional erase or programming. flash reset must be kept at v ihr (vcc 0.2v) after vcc becomes stable and while flash memory is in various operations such as programming, erase and read. other pin explanation signal name direction pin no. description xin, xout i/o 22, 23 xin and xout are used to connect crystal oscillator. porst_ i 18 this pin is used to connect reset ic for power on reset. test3 to test1 45, 20, 19 test1 to test3 are used for diagnostic test and should be kept at vcc. test7 to test4 115, 86, 47, 17 test4 to test7 are used for diagnostic test and should be open.
HN29W6484AH03TE-1 12 card block diagram flash memory flash memory flash bus a flash bus b controller pc card slot power on reset reset ic x'tal 20 mhz controller block diagram reset ic x'tal power on reset clock control h8 micro processor host interface cis, ccr task register data transfer control data buffer ecc logic flash memory interface control/status register pc card slot cis: card information structure ccr: card configuration register ecc: error correcting code flash memory note: the hitachi flash controller recover from 2-bit errors of the data field (512-byte) and 1-bit error of control field (16-byte) during read operation.
HN29W6484AH03TE-1 13 host access specifications 1. attribute access specifications when cis-rom region or configuration register region is accessed, read and write operations are executed under the condition of -reg = "l" as follows. that region can be accessed by byte/word/odd-byte modes which are defined by pc card standard specifications. attribute read access mode mode -reg -ce2 -ce1 a0 -oe -we d8 to d15 d0 to d7 standby mode h h high-z high-z byte access (8-bit) l h l l l h high-z even byte l h l h l h high-z invalid word access (16-bit) l l l l h invalid even byte odd byte access (8-bit) l l h l h invalid high-z note: : l or h attribute write access mode mode -reg -ce2 -ce1 a0 -oe -we d8 to d15 d0 to d7 standby mode h h dont care dont care byte access (8-bit) l h l l h l dont care even byte l h l h h l dont care dont care word access (16-bit) l l l h l dont care even byte odd byte access (8-bit) l l h h l dont care dont care note: : l or h attribute access timing example dout a0 to a10 -reg -ce2/-ce1 -oe -we d0 to d15 read cycle write cycle din
HN29W6484AH03TE-1 14 2. task file register access specifications there are two cases of task file register mapping, one is mapped i/o address area, the other is mapped memory address area. each case of task file register read and write operations are executed under the condition as follows. that area can be accessed by byte/word/odd byte mode which are defined by pc card standard specifications. (1) i/o address map task file register read access mode (1) mode -reg -ce2 -ce1 a0 -iord -iowr -oe -we d8 to d15 d0 to d7 standby mode h h high-z high-z byte access (8-bit) l h l l l h h h high-z even byte l h l h l h h h high-z odd byte word access (16-bit) l l l l h h h odd byte even byte odd byte access (8-bit) l l h l h h h odd byte high-z note: : l or h task file register write access mode (1) mode -reg -ce2 -ce1 a0 -iord -iowr -oe -we d8 to d15 d0 to d7 standby mode h h dont care dont care byte access (8-bit) l h l l h l h h dont care even byte l h l h h l h h dont care odd byte word access (16-bit) l l l h l h h odd byte even byte odd byte access (8-bit) l l h h l h h odd byte dont care note: : l or h task file register access timing example (1) dout a0 to a10 -reg -ce2/-ce1 -iord - iowr d0 to d15 read cycle write cycle din
HN29W6484AH03TE-1 15 (2) memory address map task file register read access mode (2) mode -reg -ce2 -ce1 a0 -oe -we -iord -iowr d8 to d15 d0 to d7 standby mode h h high-z high-z byte access (8-bit) h h l l l h h h high-z even byte h h l h l h h h high-z odd byte word access (16-bit) h l l l h h h odd byte even byte odd byte access (8-bit) h l h l h h h odd byte high-z note: : l or h task file register write access mode (2) mode -reg -ce2 -ce1 a0 -oe -we -iord -iowr d8 to d15 d0 to d7 standby mode h h dont care dont care byte access (8-bit) h h l l h l h h dont care even byte h h l h h l h h dont care odd byte word access (16-bit) h l l h l h h odd byte even byte odd byte access (8-bit) h l h h l h h odd byte dont care note: : l or h task file register access timing example (2) dout a0 to a10 -reg -ce2/-ce1 -oe -we d0 to d15 read cycle write cycle din
HN29W6484AH03TE-1 16 3. true ide mode the card can be configured in a true ide m ode of operation. this card is configured in this mode only when the -oe input signal is asserted gnd by the host. in this true ide mode attribute registers are not accessible from the host. only i/o operation to the task file and data register are allowed. if this card is configured during power on sequence, data register are accessed in word (16-bit). the card permits 8-bit accesses if the user issues a set feature command to put the device in 8-bit mode. true ide mode read i/o function mode -ce2 -ce1 a0 to a2 -iord -iowr d8 to d15 d0 to d7 invalid mode l l high-z high-z standby mode h h high-z high-z data register access h l 0 l h odd byte even byte alternate status access l h 6h l h high-z status out other task file access h l 1-7h l h high-z data note: : l or h true ide mode write i/o function mode -ce2 -ce1 a0 to a2 -iord -iowr d8 to d15 d0 to d7 invalid mode l l dont care dont care standby mode h h dont care dont care data register access h l 0 h l odd byte even byte control register access l h 6h h l dont care control in other task file access h l 1-7h h l dont care data note: : l or h true ide mode i/o access timing example dout din a0 to a2 -ce -iord -iowr -iois16 d0 to d15 read cycle write cycle
HN29W6484AH03TE-1 17 configuration register specifications this card supports four configuration registers for the purpose of the configuration and observation of this card. these registers can be used in memory card mode and i/o card mode. in true ide mode, these registers can not be used. 1. configuration option register (address 200h) this register is used for the configuration of the card configuration status and for the issuing soft reset to the card. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sreset levlreq index note: initial value: 00h name r/w function sreset (host->) r/w setting this bit to "1", places the card in the reset state (card hard reset). this operation is equal to hard reset, except this bit is not cleared. then this bit set to "0", places the card in the reset state of hard reset (this bit is set to "0" by hard reset) . card configuration status is reset and the card internal initialized operation starts when card hard reset is executed, so next access to the card should be the same sequence as the power on sequence. levlreq (host->) r/w this bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode interrupt is selected. index (host->) r/w this bits is used for select operation mode of the card as follows. when power on, card hard reset and soft reset, this data is "000000" for the purpose of memory card interface recognition. index bit assignment index bit 5 4 3 2 1 0 card mode task file register address mapping mode 0 0 0 0 0 0 memory card 0h to fh, 400h to 7ffh memory mapped 0 0 0 0 0 1 i/o card xx0h to xxfh contiguous i/o mapped 0 0 0 0 1 0 i/o card 1f0h to 1f7h, 3f6h to 3f7h primary i/o mapped 0 0 0 0 1 1 i/o card 170h to 177h, 376h to 377h secondary i/o mapped
HN29W6484AH03TE-1 18 2. configuration and status register (address 202h) this register is used for observing the card state. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chged sigchg iois8 0 0 pwd intr 0 note: initial value: 00h name r/w function chged (card->) r this bit indicates that crdy/-bsy bit on pin replacement register is set to "1". when chged bit is set to "1", -stschg pin is held "l" at the condition of sigchg bit set to "1" and the card configured for the i/o interface. sigchg (host->) r/w this bit is set or reset by the host for enabling and disabling the status-change signal (- stschg pin). when the card is configured i/o card interface and this bit is set to "1", - stschg pin is controlled by chged bit. if this bit is set to "0", -stschg pin is kept "h". iois8 (host->) r/w the host sets this field to "1" when it can provide i/o cycles only with on 8 bit data bus (d7 to d0). pwd (host->) r/w when this bit is set to "1", the card enters sleep state (power down mode). when this bit is reset to "0", the card transfers to idle state (active mode). rrdy/-bsy bit on pin replacement register becomes busy when this bit is changed. rrdy/-bsy will not become ready until the power state requested has been entered. this card automatically powers down when it is idle, and powers back up when it receives a command. intr (card->) r this bit indicates the internal state of the interrupt request. this bit state is available whether i/o card interface has been configured or not. this signal remains true until the condition which caused the interrupt request has been serviced. if interrupts are disabled by the -ien bit in the device control register, this bit is a zero.
HN29W6484AH03TE-1 19 3. pin replacement register (address 204h) this register is used for providing the signal state of -ireq signal when the card configured i/o card interface. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 crdy/-bsy 0 1 1 rrdy/-bsy 0 note: initial value: 0ch name r/w function crdy/-bsy (host->) r/w this bit is set to "1" when the rrdy/-bsy bit changes state. this bit may also be written by the host. rrdy/-bsy (host->) r/w when read, this bit indicates +ready pin states. when written, this bit is used for crdy/-bsy bit masking. 4. socket and copy register (address 206h) this register is used for identification of the card from the other cards. host can read and write this register. this register should be set by host before this card's configuration option register set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 drv# 0 0 0 0 note: initial value: 00h name r/w function drv# (host->) r/w this fields are used for the configuration of the plural cards. when host configures the plural cards, written the cards copy number in this field. in this way, host can perform the cards master/slave organization.
HN29W6484AH03TE-1 20 cis informations after the assembled flash card, cis information should be programmed into the flash. for example, cis information of hitachis flash card is defined as follows. address data 7 6 5 4 3 2 1 0 d escription of contents cis function 000h 01h cistpl_device device info tuple tuple code 002h 04h tpl_link link length is 4 byte link to next tuple 004h dfh device type w p s device speed device type = dh: i/o device wps = 1: no wp device speed = 7: ext speed device type, wps, speed 006h 4ah ext speed mantissa speed exponent 400 ns if no wait extended speed 008h 01h 1x 2k units 2k byte of address space device size 00ah ffh list end marker end of device end marker 00ch 1ch cistpl_device_oc other conditions device info tuple tuple code 00eh 04h tpl_link link length is 4 bytes link to next tuple 010h 02h ext reserved v cc mwait 3 v, wait is not used other conditions info field 012h d9h device type w p s device speed device type = dh: i/o device wps = 1: no wp device speed = 1: 250 ns device type, wps, speed 014h 01h 1x 2k units 2k byte of address space device size 016h ffh list end marker end of device end marker 018h 18h cistpl_jedec_c jedec id common memory tuple code 01ah 02h tpl_link link length is 2 bytes link to next tuple 01ch dfh pcmcias manufacturers jedec id code manufacturers id code jedec id of pc card ata 01eh 01h pcmcia jedec device code 2nd byte of jedec id 020h 20h cistpl_manfid manufacturers id code tuple code 022h 04h tpl_link link length is 4 bytes link to next tuple 024h 07h low byte of pcmcia manufacturers code hitachi jedec manufacturers id low byte of manufacturers id code 026h 00h high byte of pcmcia manufacturers code code of 0 because other byte is jedec 1 byte manufactures id high byte of manufacturers id code 028h 00h low byte of product code hitachi code for pc card ata low byte of product code 02ah 00h high byte of product code high byte of product code
HN29W6484AH03TE-1 21 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 02ch 15h cistpl_vers_1 level 1 version/product info tuple code 02eh 15h tpl_link link length is 15h bytes link to next tuple 030h 04h tpplv1_major pcmcia2.0/jeida4.1 major version 032h 01h tpplv1_minor pcmcia2.0/jeida4.1 minor version 034h 48h h info string 1 036h 49h i 038h 54h t 03ah 41h a 03ch 43h c 03eh 48h h 040h 49h i 042h 00h null terminator 044h 46h f info string 2 046h 4ch l 048h 41h a 04ah 53h s 04ch 48h h 04eh 00h null terminator 050h 34h 4 vender specific strings 052h 2eh . 054h 30h 0 056h 00h null terminator 058h ffh list end marker end of device end marker 05ah 21h cistpl_funcid function id tuple tuple code 05ch 02h tpl_link link length is 2 bytes link to next tuple 05eh 04h tplfid_function = 04h disk function, may be silicon, may be removable pc card function code 060h 01h reserved r p r = 0: no bios rom p = 1: configure card at power on system initialization byte
HN29W6484AH03TE-1 22 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 062h 22h cistpl_funce function extension tuple tuple code 064h 02h tpl_link link length is 2 bytes link to next tuple 066h 01h disk function extension tuple type disk interface type extension tuple type for disk 068h 01h disk interface type pc card ata interface interface type 06ah 22h cistpl_funce function extension tuple tuple code 06ch 03h tpl_link link length is 3 bytes link to next tuple 06eh 02h disk function extension tuple type single drive extension tuple type for disk 070h 0ch reserved d u s v no v pp , silicon, single drive v = 0: no v pp required s = 1: silicon u = 1: unique serial # d = 0: single drive on card basic ata option parameters byte 1 072h 0fh r i e n p3 p2 p1 p0 p0: sleep mode supported p1: standby mode supported p2: idle mode suppported p3: drive auto power control n: some config excludes 3x7 e: index bit is emulated i: twin iois16# data reg only r: reserved basic ata option parameters byte 2 074h 1ah cistpl_config configuration tuple tuple code 076h 05h tpl_link link length is 5 bytes link to next tuple 078h 01h rfs rms ras rfs: reserved rms: tpcc_rmsk size - 1 = 0 ras: tpcc_radr size - 1 = 1 1 byte register mask 2 byte config base address size of fields byte tpcc_sz 07ah 03h tpcc_last entry with config index of 03h is final entry in table last entry of config registers 07ch 00h tpcc_radr (lsb) configuration registers are located at 200h in reg space location of config registers 07eh 02h tpcc_radr (msb) 080h 0fh reserved s p c i i: configuration index c: configuration and status p: pin replacement s: socket and copy configuration registers present mask tpcc_rmsk
HN29W6484AH03TE-1 23 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 082h 1bh cistpl_cftable_entry configuration table entry tuple tuple code 084h 08h tpl_link link length is 8 bytes link to next tuple 086h c0h i d configuration index memory mapped i/o configuration i = 1: interface byte follows d = 1: default entry configuration index = 0 configuration table index byte tpce_indx 088h 40h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp used b = 0: bvd1 and bvd2 not used if type = 0: memory interface interface description field tpce_if 08ah a1h m ms ir io t p m = 1: misc info present ms = 01: memory space info single 2-byte length ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 08ch 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 08eh 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 090h 08h length in 256 bytes pages (lsb) length of memory space is 2 kb memory space description structures (tpce_ms) 092h 00h length in 256 bytes pages (msb) 094h 20h x r p r o a t x = 0: no more misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
HN29W6484AH03TE-1 24 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 096h 1bh cistpl_cftable_entry configuration table entry tuple tuple code 098h 06h tpl_link link length is 6 bytes link to next tuple 09ah 00h i d configuration index memory mapped i/o configuration i = 0: no interface byte d = 0: no default entry configuration index = 0 configuration table index byte tpce_indx 09ch 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 09eh 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0a0h b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 0a2h 1eh x extension +0.3 v extension byte 0a4h 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current
HN29W6484AH03TE-1 25 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 0a6h 1bh cistpl_cftable_ entry configuration table entry tuple tuple code 0a8h 0ah tpl_link link length is 10 bytes link to next tuple 0aah c1h i d configuration index contiguous i/o mapped ata registers configuration i = 1: interface byte follows d = 1: default entry configuration index = 1 configuration table index byte tpce_indx 0ach 41h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp not used b = 0: bvs1 and bvd2 not used if type = 1: i/o interface interface description field tpce_if 0aeh 99h m ms ir io t p m = 1: misc info present ms = 00: no memory space info ir = 1: interrupt info present io = 1: i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0b0h 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0b2h 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 0b4h 64h r s e io addrline s = 1: 16-bit hosts supported e = 1: 8-bit hosts supported io addrline: 4 lines decoded i/o space description field tpce_io 0b6h f0h s p l m v b i n s = 1: share logic active p = 1: pulse mode irq supported l = 1: level mode irq supported m = 1: bit mask of irqs present v = 0: no vender unique irq b = 0: no bus error irq i = 0: no io check irq n = 0: no nmi interrupt request description structure tpce_ir
HN29W6484AH03TE-1 26 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 0b8h ffh irq 7 ir q 6 ir q 5 ir q 4 ir q 3 ir q 2 ir q 1 irq0 irq level to be routed 0 to 15 recommended mask extension byte 1 tpce_ir 0bah ffh irq 15 ir q 14 ir q 13 ir q 12 ir q 11 ir q 10 ir q 9 irq8 recommended routing to any normal, maskable irq. maskextension byte 2 tpce_ir 0bch 20h x r p r o a t x = 0: nomore misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
HN29W6484AH03TE-1 27 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 0beh 1bh cistpl_cftable_entry configuration table entry tuple tuple code 0c0h 06h tpl_link link length is 6 bytes link to next tuple 0c2h 01h i d configuration index contiguous i/o mapped ata registers configuration i = 0: no interface byte d = 0: no default entry configuration index = 1 configuration table index byte tpce_indx 0c4h 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0c6h 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0c8h b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 0cah 1eh x extension +0.3 v extension byte 0cch 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current
HN29W6484AH03TE-1 28 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 0ceh 1bh cistpl_cftable_entry configuration table entry tuple tuple code 0d0h 0fh tpl_link link length is 15 bytes link to next tuple 0d2h c2h i d configuration index ata primary i/o mapped configuration i = 1: interface byte follows d = 1: default entry follows configuration index = 2 configuration table index byte tpce_indx 0d4h 41h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp not used b = 0: bvs1 and bvd2 not used if type = 1: i/o interface interface description field tpce_if 0d6h 99h m ms ir io t p m = 1: misc info present ms = 00: no memory space info ir = 1: interrupt info present io = 1: i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0d8h 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0dah 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 0dch eah r s e io addrline r = 1: range follows s = 1: 16-bit hosts supported e = 1: 8-bit hosts supported io addrlines: 10 lines decoded i/o space description field tpce_io 0deh 61h ls as n range ls = 1: size of lengths is 1 byte as = 2: size of address is 2 bytes n range = 1: address range - 1 i/o range format description
HN29W6484AH03TE-1 29 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 0e0h f0h 1st i/o base address (lsb) 1st i/o range address 0e2h 01h 1st i/o base address (msb) 0e4h 07h 1st i/o length - 1 1st i/o range length 0e6h f6h 2nd i/o base address (lsb) 2nd i/o range address 0e8h 03h 2nd i/o base address (msb) 0eah 01h 2nd i/o length - 1 2nd i/o range length 0ech eeh s p l m irq level s = 1: share logic active p = 1: pulse mode irq supported l = 1: level mode irq supported m = 0: bit mask of irqs present irq level is irq14 interrupt request description structure tpce_ir 0eeh 20h x r p r o a t x = 0: nomore misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
HN29W6484AH03TE-1 30 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 0f0h 1bh cistpl_cftable_entry configuration table entry tuple tuple code 0f2h 06h tpl_link link length is 6 bytes link to next tuple 0f4h 02h i d configuration index ata primary i/o mapped configuration i = 0: no interface byte d = 0: no default entry configuration index = 2 configuration table index byte tpce_indx 0f6h 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0f8h 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0fah b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 0fch 1eh x extension +0.3 v extension byte 0feh 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current
HN29W6484AH03TE-1 31 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 100h 1bh cistpl_cftable_entry configuration table entry tuple tuple code 102h 0fh tpl_link link length is 15 bytes link to next tuple 104h c3h i d configuration index ata secondary i/o mapped configuration i = 1: interface byte follows d = 1: default entry configuration index = 3 configuration table index byte tpce_indx 106h 41h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp not used b = 0: bvs1 and bvd2 not used if type = 1: i/o interface interface description field tpce_if 108h 99h m ms ir io t p m = 1: misc info present ms = 00: no memory space info ir = 1: interrupt info present io = 1: i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 10ah 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 10ch 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 10eh eah r s e io addrline r = 1: range follows s = 1: 16-bit hosts supported e = 1: 8-bit hosts supported io addrlines: 10 lines decoded i/o space description field tpce_io 110h 61h ls as n range ls = 1: size of lengths is 1 byte as = 2: size of address is 2 bytes n range = 1: address range - 1 i/o range format description
HN29W6484AH03TE-1 32 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 112h 70h 1st i/o base address (lsb) 1st i/o range address 114h 01h 1st i/o base address (msb) 116h 07h 1st i/o length - 1 1st i/o range length 118h 76h 2nd i/o base address (lsb) 2nd i/o range address 11ah 03h 2nd i/o base address (msb) 11ch 01h 2nd i/o length - 1 2nd i/o range length 11eh eeh s p l m irq level s = 1: share logic active p = 1: pulse mode irq supported l = 1: level mode irq supported m = 0: bit mask of irqs present irq level is irq14 interrupt request description structure tpce_ir 120h 20h x r p r o a t x = 0: nomore misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
HN29W6484AH03TE-1 33 address data 7 6 5 4 3 2 1 0 d escription of contents cis function 122h 1bh cistpl_cftable_entry configuration table entry tuple tuple code 124h 06h tpl_link link length is 6 bytes link to next tuple 126h 03h i d configuration index ata secondary i/o mapped configuration i = 0: no interface byte d = 0: no default entry configuration index = 3 configuration table index byte tpce_indx 128h 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 12ah 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 12ch b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 12eh 1eh x extension +0.3 v extension byte 130h 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current 132h 14h cistpl_no_link no link control tuple tuple code 134h 00h link is 0 bytes link to next tuple 136h ffh cistpl_end end of list tuple tuple code
HN29W6484AH03TE-1 34 task file register specification these registers are used for reading and writing the storage data in this card. these registers are mapped five types by the configuration of index in configuration option register. the decoded addresses are shown as follows. memory map (index = 0) -reg a10 a9 to a4 a3 a2 a1 a0 offset -oe = l -we = l 1 0 0 0 0 0 0h data register data register 1 0 0 0 0 1 1h error register feature register 1 0 0 0 1 0 2h sector count register sector count register 1 0 0 0 1 1 3h sector number register sector number register 1 0 0 1 0 0 4h cylinder low register cylinder low register 1 0 0 1 0 1 5h cylinder high register cylinder high register 1 0 0 1 1 0 6h drive head register drive head register 1 0 0 1 1 1 7h status register command register 1 0 1 0 0 0 8h dup. even data register dup. even data register 1 0 1 0 0 1 9h dup. odd data register dup. odd data register 1 0 1 1 0 1 dh dup. error register dup. feature register 1 0 1 1 1 0 eh alt. status register device control register 1 0 1 1 1 1 fh drive address register reserved 1 1 0 8h even data register even data register 1 1 1 9h odd data register odd data register
HN29W6484AH03TE-1 35 contiguous i/o map (index = 1) -reg a10 to a4 a3 a2 a1 a0 offset -iord = l -iowr = l 0 0 0 0 0 0h data register data register 0 0 0 0 1 1h error register feature register 0 0 0 1 0 2h sector count register sector count register 0 0 0 1 1 3h sector number register sector number register 0 0 1 0 0 4h cylinder low register cylinder low register 0 0 1 0 1 5h cylinder high register cylinder high register 0 0 1 1 0 6h drive head register drive head register 0 0 1 1 1 7h status register command register 0 1 0 0 0 8h dup. even data register dup. even data register 0 1 0 0 1 9h dup. odd data register dup. odd data register 0 1 1 0 1 dh dup. error register dup. feature register 0 1 1 1 0 eh alt. status register device control register 0 1 1 1 1 fh drive address register reserved primary i/o map (index = 2) -reg a10 a9 to a4 a3 a2 a1 a0 -iord = l -iowr = l 0 1fh 0 0 0 0 data register data register 0 1fh 0 0 0 1 error register feature register 0 1fh 0 0 1 0 sector count register sector count register 0 1fh 0 0 1 1 sector number register sector number register 0 1fh 0 1 0 0 cylinder low register cylinder low register 0 1fh 0 1 0 1 cylinder high register cylinder high register 0 1fh 0 1 1 0 drive head register drive head register 0 1fh 0 1 1 1 status register command register 0 3fh 0 1 1 0 alt. status register device control register 0 3fh 0 1 1 1 drive address register reserved
HN29W6484AH03TE-1 36 secondary i/o map (index = 3) -reg a10 a9 to a4 a3 a2 a1 a0 -iord = l -iowr = l 0 17h 0 0 0 0 data register data register 0 17h 0 0 0 1 error register feature register 0 17h 0 0 1 0 sector count register sector count register 0 17h 0 0 1 1 sector number register sector number register 0 17h 0 1 0 0 cylinder low register cylinder low register 0 17h 0 1 0 1 cylinder high register cylinder high register 0 17h 0 1 1 0 drive head register drive head register 0 17h 0 1 1 1 status register command register 0 37h 0 1 1 0 alt. status register device control register 0 37h 0 1 1 1 drive address register reserved true ide mode i/o map -ce2 -ce1 a2 a1 a0 -iord = l -iowr = l 1 0 0 0 0 data register data register 1 0 0 0 1 error register feature register 1 0 0 1 0 sector count register sector count register 1 0 0 1 1 sector number register sector number register 1 0 1 0 0 cylinder low register cylinder low register 1 0 1 0 1 cylinder high register cylinder high register 1 0 1 1 0 drive head register drive head register 1 0 1 1 1 status register command register 0 1 1 1 0 alt. status register device control register 0 1 1 1 1 drive address register reserved
HN29W6484AH03TE-1 37 1. data register: this register is a 16-bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. this register can be accessed in word mode and byte mode. this register overlaps the error or feature register. bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d0 to d15 2. error register: this register is a read only register, and it is used for analyzing the error content at the card accessing. this register is valid when the bsy bit in status register and alternate status register are set to "0" (ready). bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bbk unc 0 idnf 0 abrt 0 amnf bit name function 7 bbk (bad block detected) this bit is set when a bad block is detected in requested id field. 6 unc (data ecc error) this bit is set when uncorrectable error is occurred at reading the card. 4 idnf (id not found) the requested sector id is in error or cannot be found. 2 abrt (aborted command) this bit is set if the command has been aborted because of the card status condition. (not ready, write fault, invalid command, etc.) 0 amnf (address mark not found) this bit is set in case of a general error. 3. feature register: this register is write only register, and provides information regarding features of the drive which the host wishes to utilize. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 feature byte 4. sector count register: this register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. if the value of this register is zero, a count of 256 sectors is specified. in plural sector transfer, if not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request. this register's initial value is "01h". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sector count byte
HN29W6484AH03TE-1 38 5. sector number register: this register contains the starting sector number which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sector number byte 6. cylinder low register: this register contains the low 8-bit of the starting cylinder address which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cylinder low byte 7. cylinder high register: this register contains the high 8-bit of the starting cylinder address which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cylinder high byte 8. drive head register: this register is used for selecting the drive number and head number for the following command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 lba 1 drv head number bit name function 7 1 this bit is set to "1". 6 lba lba is a flag to select either cylinder / head / sector (chs) or logical block address (lba) mode. when lba=0, chs mode is selected. when lba=1, lba mode is selected. in lba mode, the logical block address is interrupted as follows: lba07-lba00 : sector number register d7-d0. lba15-lba08 : cylinder low register d7-d0. lba23-lba16 : cylinder high register d7-d0. lba27-lba24 : drive / head register bits hs3-hs0. 5 1 this bit is set to "1". 4 drv (drive select) this bit is used for selecting the master (card 0) and slave (card 1) in master/slave organization. the card is set to be card 0 or 1 by using drv# of the socket and copy register. 3 to 0 head number this bit is used for selecting the head number for the following command. bit 3 is msb. 9. status register: this register is read only register, and it indicates the card status of command execution. when this register is read in configured i/o card mode (index = 1, 2, 3) and level interrupt mode, -ireq is
HN29W6484AH03TE-1 39 negated. this register should be accessed in byte mode. in word mode, it is recommended that alternate status register may be used as this register. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bsy drdy dwf dsc drq corr idx err bit name function 7 bsy (busy) this bit is set when the card internal operation is executing. when this bit is set to "1", other bits in this register are invalid. 6 drdy (drive ready) if this bit and dsc bit are set to "1", the card is capable of receiving the read or write or seek requests. if this bit is set to "0", the card prohibits these requests. 5 dwf (drive write fault) this bit is set if this card indicates the write fault status. 4 dsc (drive seek complete) this bit is set when the drive seek complete. 3 drq (data request) this bit is set when the information can be transferred between the host and data register. this bit is cleared when the card receives the other command. 2 corr (corrected data) this bit is set when a correctable data error has been occurred and the data has been corrected. 1 idx (index) this bit is always set to "0". 0 err (error) this bit is set when the previous command has ended in some type of error. the error information is set in the other status register or error register. this bit is cleared by the next command. 10. alternate status register: this register is the same as status register in physically, so the bit assignment refers to previous item of status register. but this register is different from status register that -ireq is not negated when data read. 11. command register: this register is write only register, and it is used for writing the command at executing the drive operation. the command code written in the command register, after the parameter is written in the task file during the card is ready state.
HN29W6484AH03TE-1 40 used parameter command command code fr sc sn cy dr hd lba check power mode e5h or 98h n n n n y n n execute drive diagnostic 90h n n n n y n n erase sector c0h n y y y y y y format track 50h n y n y y y y identify drive ech n n n n y n n idle e3h or 97h n y n n y n n idle immediate e1h or 95h n n n n y n n initialize drive parameters 91h n y n n y y n read buffer e4h n n n n y n n read multiple c4h n y y y y y y read long sector 22h or 23h n n y y y y y read sector 20h or 21h n y y y y y y read verify sector 40h or 41h n y y y y y y recalibrate 1xh n n n n y n n request sense 03h n n n n y n n seek 7xh n n y y y y y set features efh y n n n y n n set multiple mode c6h n y n n y n n set sleep mode e6h or 99h n n n n y n n stand by e2h or 96h n n n n y n n stand by immediate e0h or 94h n n n n y n n translate sector 87h n y y y y y y wear level f5h n n n n y y n write buffer e8h n n n n y n n write long sector 32h or 33h n n y y y y y write multiple c5h n y y y y y y write multiple w/o erase cdh n y y y y y y write sector 30h or 31h n y y y y y y write sector w/o erase 38h n y y y y y y write verify 3ch n y y y y y y note: fr: feature register sc: sector count register sn: sector number register cy: cylinder register dr: drv bit of drive head register hd: head number of drive head register lba: logical block address mode supported y: the register contains a valid parameter for this command. n: the register does not contain a valid parameter for this command.
HN29W6484AH03TE-1 41 12. device control register: this register is write only register, and it is used for controlling the card interrupt request and issuing an ata soft reset to the card. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 srst nien 0 bit name function 7 to 4 don't care 3 1 this bit is set to "1". 2 srst (software reset) this bit is set to "1" in order to force the card to perform task file reset operation. this does not change the card configuration registers as a hardware reset does. the card remains in reset until this bit is reset to "0". 1 nien (interrupt enable) this bit is used for enabling -ireq. when this bit is set to "0", - ireq is enabled. when this bit is set to "1", -ireq is disabled. 0 0 this bit is set to "0". 13. drive address register: this register is read only register, and it is used for confirming the drive status. this register is provides for compatibility with the at disk drive interface. it is recommended that this register is not mapped into the hosts i/o space because of potential conflicts on bit7. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 nwtg nhs3 nhs2 nhs1 nhs0 nds1 nds0 bit name function 7 this bit is unknown 6 nwtg (writing gate) this bit is unknown 5 to 2 nhs3-0 (head select3-0) these bits is the negative value of head select bits (bit 3 to 0) in drive/head register. 1 nds1 (idrive select1) this bit is unknown 0 nds0 (idrive select0) this bit is unknown
HN29W6484AH03TE-1 42 ata command specifications this table summarizes the ata command set with the paragraphs. following shows the support commands and command codes which are written in command registers. ata command set no. command set code fr sc sn cy dr hd lba 1 check power mode e5h or 98h y 2 execute drive diagnostic 90h y 3 erase sector(s) c0h y y y y y y 4 format track 50h y y y y y 5 identify drive ech y 6 idle e3h or 97h y y 7 idle immediate e1h or 95h y 8 initialize drive parameters 91h y y y 9 read buffer e4h y 10 read multiple c4h y y y y y y 11 read long sector 22h, 23h y y y y y 12 read sector (s) 20h, 21h y y y y y y 13 read verify sector (s) 40h, 41h y y y y y y 14 recalibrate 1xh y 15 request sense 03h y 16 seek 7xh y y y y y 17 set features efh y y 18 set multiple mode c6h y y 19 set sleep mode e6h or 99h y 20 stand by e2h or 96h y 21 stand by immediate e0h or 94h y 22 translate sector 87h y y y y y y 23 wear level f5h y y 24 write buffer e8h y 25 write long sector 32h or 33h y y y y y 26 write multiple c5h y y y y y y 27 write multiple w/o erase cdh y y y y y y 28 write sector 30h or 31h y y y y y y 29 write sector(s) w/o erase 38h y y y y y y 30 write verify 3ch y y y y y y
HN29W6484AH03TE-1 43 note: fr: feature register sc: sector count register (00h to ffh) sn: sector number register (01h to 20h) cy: cylinder low/high register (to) dr: drive bit of drive/head register hd: head no.(0 to 3) of drive/head register nh: no. of heads y: set up : not set up 1. check power mode (code: e5h or 98h): this command checks the power mode. 2. execute drive diagnostic (code: 90h): this command performs the internal diagnostic tests implemented by the card. 3. erase sector(s) (code: c0h): this command is used to erase data sectors. 4. format track (code: 50h): this command writes the desired head and cylinder of the selected drive. but selected sector data is not exchange. this card excepts a sector buffer of data from the host to follow the command with same protocol as the write sector command. 5. identify drive (code: ech): this command enables the host to receive parameter information from the card.
HN29W6484AH03TE-1 44 identify drive information word address default value total bytes data field type information 0 848ah 2 general configuration bit-significant information 1 xxxx 2 default number of cylinders 2 0000h 2 reserved 3 00xxh 2 default number of heads 4 0000h 2 number of unformatted bytes per track 5 xxxx 2 number of unformatted bytes per sector 6 xxxx 2 default number of sectors per track 7 to 8 xxxx 4 number of sectors per card (word7 = msw, word8 = lsw) 9 0000h 2 reserved 10 to 19 xxxx 20 reserved 20 0002h 2 buffer type (dual ported) 21 0002h 2 buffer size in 512 byte increments 22 0004h 2 # of ecc bytes passed on read/write long commands 23 to 46 xxxx 48 firmware revision in ascii etc. 47 0001h 2 maximum of 1 sector on read/write multiple command 48 0000h 2 double word not supported 49 0200h 2 capabilities: dma not supported (bit 8), lba supported (bit9) 50 0000h 2 reserved 51 0100h 2 pio data transfer cycle timing m ode 1 52 0000h 2 dma data transfer cycle timing m ode not supported 53 to 58 xxxx 12 reserved 59 010xh 2 multiple sector setting is valid 60 to 61 xxxx 4 total number of sectors addressable in lba mode 62 to 127 0000h 138 reserved 128 to 159 xxxxh 64 reserved vendor unique bytes 160 to 255 0000h 192 reserved 6. idle (code: e3h or 97h): this command causes the card to set bsy, enter the idle mode, clear bsy and generate an interrupt. if sector count is non-zero, the automatic power down mode is enabled. if the sector count is zero, the automatic power down mode is disabled. 7. idle immediate (code: e1h or 95h): this command causes the card to set bsy, enter the idle (read) mode, clear bsy and generate an interrupt. 8. initialize drive parameters (code: 91h): this command enables the host to set the number of sectors per track and the number of heads per cylinder.
HN29W6484AH03TE-1 45 9. read buffer (code: e4h): this command enables the host to read the current contents of the card's sector buffer. 10. read multiple (code: c4h): this command performs similarly to the read sectors command. interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a set multiple command. 11. read long sector (code: 22h or 23h): this command performs similarly to the read sector(s) command except that it returns 516 bytes of data instead of 512 bytes. 12. read sector(s) (code: 20h, 21h): this command reads from 1 to 256 sectors as specified in the sector count register. a sector count of 0 requests 256 sectors. the transfer begins at the sector specified in the sector number register. 13. read verify sector(s) (code: 40h or 41h): this command is identical to the read sectors command, except that drq is never set and no data is transferred to the host . 14. recalibrate (code: 1xh): this command is effectively a nop command to the card and is provided for compatibility purposes. 15. request sense (code: 03h): this command requests an extended error code after command ends with an error. 16. seek (code: 7xh): this command is effectively a nop command to the card although it does perform a range check. 17. set features (code: efh): this command is used by the host to establish or select certain features. feature operation 01h enable 8-bit data transfers. 55h disable read look ahead. 66h disable power on reset (por) establishment of defaults at soft reset. 81h disable 8-bit data transfers. bbh 4 bytes of data apply on read/write long commands. cch enable power on reset (por) establishment of defaults at soft reset. 18. set multiple mode (code: c6h): this command enables the card to perform read and write multiple operations and establishes the block count for these commands. 19. set sleep mode (code: e6h or 99h): this command causes the card to set bsy, enter the sleep mode, clear bsy and generate an interrupt. 20. stand by (code: e2h or 96h): this command causes the card to set bsy, enter the sleep mode (which corresponds to the ata "standby" mode), clear bsy and return the interrupt immediately. 21. stand by immediate (code: e0h or 94h): this command causes the card to set bsy, enter the sleep mode(which corresponds to the ata "standby" mode), clear bsy and return the interrupt immediately.
HN29W6484AH03TE-1 46 22. translate sector (code: 87h): this command allows the host a method of determining the exact number of times a user sector has been erased and programmed. 23. wear level (code: f5h): this command effectively a nop command and only implemented for backward compatibility. the sector count register will always be returned with an 00h indicating wear level is not needed. 24. write buffer (code: e8h): this command enables the host to overwrite contents of the card's sector buffer with any data pattern desired. 25. write long sector (code: 32h or 33h): this command is provided for compatibility purposes and is similar to the write sector(s) command except that it writes 516 bytes instead of 512 bytes. 26. write multiple (code: c5h): this command is similar to the write sectors command. interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by set multiple command. 27. write multiple without erase (code: cdh): this command is similar to the write multiple command with the exception that an implied erase before write operation is not performed. 28. write sector(s) (code: 30h or 31h): this command writes from 1 to 256 sectors as specified in the sector count register. a sector count of zero requests 256 sectors. the transfer begins at the sector specified in the sector number register. 29. write sector(s) without erase (code: 38h): this command is similar to the write sector(s) command with the exception that an implied erase before write operation is not performed. 30. write verify (code: 3ch): this command is similar to the write sector(s) command, except each sector is verified immediately after being written.
HN29W6484AH03TE-1 47 sector transfer protocol 1. sector read: 1 sector read procedure after the card configured i/o interface is shown as follows. start set the cylinder low / high register set the head no. of drive head register set the sector number register set "01h" in sector count register set "20h" in command register read the status register "58h"? read 256 times the data register (512 bytes) read the status register "50h"? wait the command input i/o access, index=1 (2) (3) (4)burst data transfer (5) y y n n (1)set the logical sector number
HN29W6484AH03TE-1 48 a0 to a10 -ce1 -ce2 -iowr -iord d0 to d15 -ireq (1) (2) (3) (4) (5) 4h 5h 6h 3h 2h 7h 7h 7h 0h 0h 7h 7h 01h20h 80h 58h 50h 80h data transfer
HN29W6484AH03TE-1 49 2. sector write: 1 sector write procedure after the card configured i/o interface is shown as follows. start set the cylinder low / high register set the head no. of drive head register set the sector number register set "01h" in sector count register set "30h" in command register read the status register "58h"? write 256 times the data register (512 bytes) read the status register "50h"? wait the command input i/o access, index=1 (2) (3) (4) burst data transfer (5) y y n n (1) set the logical sector number
HN29W6484AH03TE-1 50 a0 to a10 -ce1 -ce2 -iowr -iord d0 to d15 -ireq (1) (2) (3) (4) (5) 4h 5h 6h 3h 2h 7h 7h 7h 0h 0h 7h 7h 01h30h 80h 58h 50h 80h data transfer
HN29W6484AH03TE-1 51 absolute maximum ratings parameter symbol value unit note all input/output voltages vin, vout C0.3 to v cc + 0.3 v 1 v cc voltage v cc C0.3 to +6.7 v operating temperature range topr C40 to +85 ?c storage temperature range tstg C55 to +125 ?c note: 1. vin, vout min = C2.0 v for pulse width ? 20 ns. recommended operating conditions parameter symbol min typ max unit operating temperature ta 0 25 70 ?c v cc voltage v cc 4.5 5.0 5.5 v 3.15 3.3 3.45 v capacitance (ta = 25c, f = 1mhz) parameter symbol min typ max unit test conditions note input capacitance cin 15 pf vin = 0 v 1 output capacitance cout 15 pf vout = 0 v 1 note: 1. this parameter is sampled and not 100% tested. card system performance item performance set up times (reset to ready) 100 ms (max) set up times (sleep to idle) 2 ms (max) data transfer rate to/from host 8 mb/s burst controller overhead (command to drq) 2 ms (max) data transfer cycle end to ready (sector write) 1.2 ms (typ)
HN29W6484AH03TE-1 52 dc characteristics-1 (ta = 0 to +70c, v cc = 3.3 v 5 % ) parameter symbol min typ max unit test conditions input voltage (cmos level) v ihc 0.7 v cc v cc + 0.3 v v ilc C0.3 0.2 v cc v input voltage (ttl level) v ihc 2.0 v cc + 0.3 v v ilc C0.3 0.6 v schmitt circuit (cmos level)* 1 v tc+ (1.6) 2.6 v v cc = 3.3 v v tc C 0.7 (1.7) v v tc * 2 (0.3) v output voltage (cmos) (2 ma)* 3 v oh v cc C 0.4 v i oh = C2 ma v ol 0.4 v i ol = 2 ma output voltage (cmos) (3 ma)* 3 v oh v cc C 0.4 v i oh = C3 ma v ol 0.4 v i ol = 3 ma output voltage (cmos) (2 ma/3 ma)* 3 v oh v cc C 0.4 v i oh = C2 ma v ol 0.4 v i ol = 3 ma output voltage (cmos) (1 ma/2 ma)* 3 v oh v cc C 0.4 v i oh = C1 ma v ol 0.4 v i ol = 2 ma input leakage current* 4 i li 1 a output leakage current* 4 i lo 1 a v out = high impedance pull-up current/(resistivity) Ci pu 15/(230) 80/(41) 230/(13.7) a/(k w ) v in = gnd pull-up current/(resistivity)* 5 Ci pu 2/(1800) 16/(206) 36/(85) a/(k w ) v in = gnd sleep/standby current* 8 i sp1 (0.2) (0.5) ma cmos level (control signal = v cc C 0.2) (in memory card mode and i/o card mode) sector read current* 6, 8 i ccr (dc) (25) (50) ma cmos level (control signal = v cc C 0.2) i ccr (peak) (50) (80) ma sector write current* 7, 8 i ccw (dc) (25) (50) ma cmos level (control signal = v cc C 0.2) i ccw (peak) (50) (80) ma
HN29W6484AH03TE-1 53 dc characteristics-2 (ta = 0 to +70c, v cc = 5 v 10%) parameter symbol min typ max unit test conditions input voltage (cmos level) v ihc 0.7 v cc v cc + 0.3 v v ilc C0.3 0.3 v cc v input voltage (ttl level) v ihc 2.4 v cc + 0.3 v v ilc C0.3 0.6 v schmitt circuit (cmos level)* 1 v tc+ (2.8) 4.0 v v cc = 5 v v tc C 1.1 (2.4) v v tc * 2 (0.3) v output voltage (cmos) (2 ma)* 3 v oh v cc C 0.4 v i oh = C4 ma v ol 0.4 v i ol = 4 ma output voltage (cmos) (3 ma)* 3 v oh v cc C 0.4 v i oh = C8 ma v ol 0.4 v i ol = 8 ma output voltage (cmos) (2 ma/3 ma)* 3 v oh v cc C 0.4 v i oh = C6 ma v ol 0.4 v i ol = 8 ma output voltage (cmos) (1 ma/2 ma)* 3 v oh v cc C 0.4 v i oh = C3 ma v ol 0.4 v i ol = 4 ma input leakage current* 4 i li 1 a output leakage current* 4 i lo 1 a v out = high impedance pull-up current/(resistivity) Ci pu 60/(92) 220/(23) 570/(7.9) a/(k w ) v in = gnd pull-up current/(resistivity)* 5 Ci pu 10/(550) 45/(110) 90/(50) a/(k w ) v in = gnd sleep/standby current* 8 i sp1 (0.5) (1.0) ma cmos level (control signal = v cc C 0.2) (in memory card mode and i/o card mode) sector read current* 6, 8 i ccr (dc) (40) (70) ma cmos level (control signal = v cc C 0.2) i ccr (peak) (80) (120) ma sector write current* 7, 8 i ccw (dc) (45) (75) ma cmos level (control signal = v cc C 0.2) i ccw (peak) (80) (120) ma
HN29W6484AH03TE-1 54 notes : 1. cmos schmitt input is measured at v ih = v tc+ max and v il = v tc C mim. ( ) is reference value. 2. v tc is reference value. 3. measured for static state. 4. except pulled up input/output pin. 5. pull-up resister is 100 k w . 6. measured during sector read transfer. 7. measured during sector write transfer. 8. power dissipation is reference value on the assembled flash card, including the flash memory.
HN29W6484AH03TE-1 55 dc current waveform (v cc = 5 v, ta = 25?c) power on operation (reference only) power on time dc current
HN29W6484AH03TE-1 56 sector read 0 current i cc r(peak) i cc r(dc) time command write complete of sector read sector write 0 current i cc w(peak) i cc w(dc) time command write complete of sector write
HN29W6484AH03TE-1 57 ac characteristics (ta = 0 to +70?c, v cc = 5 v 10%, v cc = 3.3 v 5%) attribute memory read ac characteristics 250 ns parameter symbol min typ max unit read cycle time tcr 250 ns address access time ta(a) 250 ns -ce access time ta(ce) 250 ns -oe access time ta(oe) 125 ns output disable time (-ce) tdis(ce) 100 ns output disable time (-oe) tdis(oe) 100 ns output enable time (-ce) ten(ce) 5 ns output enable time (-oe) ten(oe) 5 ns data valid time (a) tv(a) 0 ns address setup time tsu(a) 30 ns address hold time th(a) 20 ns -ce setup time t su(ce) 0 ns -ce hold time t h(ce) 20 ns attribute memory read timing t h(a) t v(a) t dis(ce) t dis(oe) t h(ce) valid output t su(ce) t su(a) t cr a0 to a10 -reg -ce2/-ce1 -oe d0 to d15 -we, -iowr, -iord : high fix t a(a) t a(ce) t a(oe) t en(oe) t en(ce)
HN29W6484AH03TE-1 58 attribute memory write ac characteristics 250 ns parameter symbol min typ max unit write cycle time tcw 250 ns write pulse time tw(we) 150 ns address setup time tsu(a) 30 ns address setup time (-we) tsu(a-weh) 180 ns -ce setup time (-we) tsu(ce-weh) 180 ns data setup time (-we) tsu(d-weh) 80 ns data hold time th(d) 30 ns write recover time trec(we) 30 ns output disable time (-we) tdis(we) 100 ns output disable time (-oe) tdis(oe) 100 ns output enable time (-we) ten(we) 5 ns output enable time (-oe) ten(oe) 5 ns output enable setup time (-we) tsu(oe-we) 10 ns output enable hold time (-we) th(oe-we) 10 ns -ce setup time t su(ce) 0 ns -ce hold time t h(ce) 20 ns attribute memory write timing a0 to a10 -reg -ce2/-ce1 -oe d0 to d15(din) d0 to d15(dout) t su(ce) t su(d-weh) i nput data t dis(we) t dis(oe) t en(we) t en(oe) t h(d) t h(oe-we) t rec(we) t h(ce) t su(oe-we) t su(a) -iowr, -iord : high fix -we t cw t su(ce-weh) t su(a-weh) t w(we)
HN29W6484AH03TE-1 59 i/o access read ac characteristics parameter symbol min typ max unit data delay after -iord td(iord) 100 ns data hold following -iord th(iord) 0 ns -iord pulse width tw(iord) 165 ns address setup before -iord tsua(iord) 70 ns address hold following -iord tha(iord) 20 ns -ce setup before -iord tsuce(iord) 5 ns -ce hold following -iord thce(iord) 20 ns -reg setup before -iord tsureg(iord) 5 ns -reg hold following -iord threg(iord) 0 ns -inpack delay falling from -iord tdfinpcak(iord) 0 45 ns -inpack delay rising from -iord tdrinpack(iord) 45 ns -iois16 delay falling from address tdfiois16(adr) 35 ns -iois16 delay rising from address tdriois16(adr) 35 ns i/o access read timing -reg a0 to a10 -ce2/-ce1 -we, -oe, -iowr : high fix d0 to d15 -iord t sureg(iord) t suce(iord) t ha(iord) t hreg(iord) t hce(iord) t sua(iord) t dfiois16(adr) t dfinpack(iord) t drinpack(iord) t driois16(adr) t h(iord) valid output t d(iord) -inpack -iois16 t w(iord)
HN29W6484AH03TE-1 60 i/o access write ac characteristics parameter symbol min typ max unit data setup before -iowr tsu(iowr) 60 ns data hold following -iowr th(iowr) 30 ns -iowr pulse width tw(iowr) 165 ns address setup before -iowr tsua(iowr) 70 ns address hold following -iowr tha(iowr) 20 ns -ce setup before -iowr tsuce(iowr) 5 ns -ce hold following -iowr thce(iowr) 20 ns -reg setup before -iowr tsureg(iowr) 5 ns -reg hold following -iowr threg(iowr) 0 ns -iois16 delay falling from address tdfiois16(adr) 35 ns -iois16 delay rising from address tdriois16(adr) 35 ns i/o access write timing -we, -oe, -iord : high fix d0 to d15 -reg a0 to a10 -ce2/-ce1 -iowr t sureg(iowr) t suce(iowr) t ha(iowr) t hreg(iowr) t hce(iowr) t sua(iowr) t su(iowr) t dfiois16(adr) t driois16(adr) t h(iowr) -iois16 t w(iowr) data in
HN29W6484AH03TE-1 61 common memory access read ac characteristics parameter symbol min typ max unit -oe access time ta(oe) 125 ns output disable time (-oe) tdis(oe) 100 ns address setup time tsu(a) 30 ns address hold time th(a) 20 ns -ce setup time tsu(ce) 0 ns -ce hold time th(ce) 20 ns common access read timing -reg a0 to a10 -ce2/-ce1 -oe valid output d0 to d15 -we, -iord, -iowr : high fix t su(a) t h(a) t h(ce) t su(ce) t dis(oe) t a(oe)
HN29W6484AH03TE-1 62 common memory access write ac characteristics parameter symbol min typ max unit data setup time (-we) tsu(d-weh) 80 ns data hold time th(d) 30 ns write pulse time tw(we) 150 ns address setup time tsu(a) 30 ns -ce setup time tsu(ce) 0 ns write recover time trec(we) 30 ns -ce hold following -we th(ce) 20 ns common access write timing -reg a0 to a10 -ce2/-ce1 -we data in d0 to d15 -iowr, -iord, -oe : high fix t h(d) t su(a) t w(we) t su(ce) t h(ce) t rec(we) t su(d-weh)
HN29W6484AH03TE-1 63 true ide mode access read ac characteristics parameter symbol min typ max unit data delay after iord td(iord) 100 ns data hold following iord th(iord) 0 ns iord width time tw(iord) 165 ns address setup before iord tsua(iord) 70 ns address hold following iord tha(iord) 20 ns ce setup before iord tsuce(iord) 5 ns ce hold following iord thce(iord) 20 ns iois16 delay falling from address tdfiois16(adr) 35 ns iois16 delay rising from address tdfiois16(adr) 35 ns true ide mode access read timing -iord a0 to a2 -ce2/-ce1 -iois16 valid output d0 to d15 -iowr: high fix, -oe: low fix, -we: high fix t sua(iord) t suce(iord) t ha(iord) t hce(iord) t h(iord) t drlois(adr) t drlois(adr) t d(iord) t w(iord)
HN29W6484AH03TE-1 64 true ide mode a ccess write ac characteristics parameter symbol min typ max unit data setup before iowr tsu(iowr) 60 ns data hold following iowr th(iowr) 30 ns iord width time tw(iowr) 165 ns address setup before iowr tsua(iowr) 70 ns address hold following iowr tha(iowr) 20 ns ce setup before iowr tsuce(iowr) 5 ns ce hold following iowr thce(iowr) 20 ns iois16 delay falling from address tdfiois16(adr) 35 ns iois16 delay rising from address tdfiois16(adr) 35 ns true ide mode access write timing -iowr a0 to a2 -ce2/-ce1 -iois16 valid output d0 to d15 -iord: high fix, -oe: low fix, -we: high fix t sua(iowr) t suce(iowr) t ha(iowr) t hce(iowr) t h(iowr) t drlois(adr) t drlois(adr) t su(iowr) t w(iowr)
HN29W6484AH03TE-1 65 flash memory interface ac characteristics (ta = 0 to +70c, v cc = 5 v 10%, 3.3 v 5%) parameter symbol min typ max unit write pulse time t wp 60 ns write pulse high time t wph 40 ns f_cde_ setup time for f_we_ t cds 0 ns data setup time t ds 50 ns data hold time t dh 10 ns address setup time t as 50 ns address hold time t ah 10 ns f_oe_ setup time for f_sc t oes 0 ns f_oe_ low to output low-z t oel 0 ns f_cde_ setup time for f_sc t cdss 100 ns serial clock cycle time t scc 50 ns f_sc pulse width t sp 20 ns f_sc pulse low time t spl 20 ns f_sc to output delay t sac 50 ns f_sc to output hold t sh 15 ns data setup time for f_sc t sds 0 ns data hold time for f_sc t sdh 30 ns f_oe_ to output delay t oe 60 ns f_oe_ high to output flat t df 40 ns time to device busy t db 150 ns
HN29W6484AH03TE-1 66 flash memory interface timing t cds t oes t oel t sac t oe t df t db t oe t df t sac t sdh t sh t sds t scc t scc t sp t sp t spl t spl t cdss t scc t wp t wph t wp t cds t as t ah t ds t dh f_we_ f_cde_ f_d0 to f_d7 f_oe_ f_cde_ f_sc d_d0 to f_d7 f_oe_ f_cde_ f_d0 to f_d7 f_we_ f_d0 to f_d7 f_rdy flash command write timing flash address write timing flash command write timing flash command write timing flash command write timing flash command write timing flash command write timing note: f_oe_ : connect to f_oea_ or f_oeb_ . f_we_ : connect to f_wea_ and f_web_ . f_cde_ : connect to f_cdea_ and f_cdeb_ . f_sc : connect to f_sc_1a, f_sc_2a or f_sc_1b, f_sc_2b. f_d0 to f_d7 : connect to f_da_0 to f_da7 and f_db_0 to f_db7 . f_rdy_ : connect to f_rdy_1 and f_rdy_2.
HN29W6484AH03TE-1 67 reset characteristics (only memory card mode or i/o card mode) hard reset characteristics parameter symbol min typ max unit test conditions reset setup time tsu(reset) 100 ms -ce recover time trec(vcc) 1 s vcc rising up time tpr 0.1 100 ms vcc falling down time tpf 3 300 ms reset pulse width tw(reset) 10 s th(hi-zreset) 1 ms ts(hi-zreset) 0 ms hard reset timing v cc -ce1, -ce2 t pr t pf 10% 90% 10% 90% t h(hi-zreset) t s(hi-zreset) t su(reset) t w(reset) low high-z high-z t rec( v cc) reset
HN29W6484AH03TE-1 68 power on reset characteristics power on reset sequence must need by -porst at the rising of v cc . parameter symbol min typ max unit test conditions -ce setup time tsu(vcc) 100 ms vcc rising up time tpr 0.1 100 ms power on reset timing t pr t su( v cc) v cc -porst -ce1, -ce2 attention for card use in the reset or power off, all register informations are cleared. notice that the card insertion/removal should not be executed during host is active, if the card is used in true ide mode. after the card hard reset, soft reset, or power on reset, ata reset, command applied the card cannot access during +rdy/- bsy pin is "low" level. flash card cant be operated in this case. notice that the card removal should be executed after card internal operations completed. before the card insertion v cc can not be supplied to the card. after confirmation that -cd1, -cd2 pins are inserted, supply v cc to the card. -oe must be kept at the v cc level during power on reset in memory card mode and i/o card mode. -oe must be kept constantly at the gnd level in true ide mode.
HN29W6484AH03TE-1 69 physical outline 0.07 m 1.20 *0.17 0.05 0.15 0.04 16.0 0.2 16.0 0.2 14 0.4 90 61 130 120 91 31 60 *0.17 0.05 0.15 0.04 0 ?8? 0.10 1.00 1.20 max 0.10 0.10 1.0 0.5 0.1 unit: mm *dimension including the plating thickness basematerial dimension
HN29W6484AH03TE-1 70 schematic flash card (reference only) f_oea_ f_wea_ f_cdea_ f_da(0) f_da(1) f_da(2) f_da(3) f_da(4) f_da(5) f_da(6) f_da(7) f_sc_a1 f_sc_a2 f_oeb_ f_web_ f_cdeb_ f_db(0) f_db(1) f_db(2) f_db(3) f_db(4) f_db(5) f_db(6) f_db(7) f_res f_sc_b1 f_sc_b2 f_rdy_1 f_rdy_2 f_cea_1 f_cea_2 f_cea_3 f_cea_4 f_cea_5 f_cea_6 f_cea_7 f_cea_8 f_cea_9 f_cea_10 f_ceb_1 f_ceb_2 f_ceb_3 f_ceb_4 f_ceb_5 f_ceb_6 f_ceb_7 f_ceb_8 f_ceb_9 f_ceb_10 83 72 84 82 80 79 78 77 75 74 73 60 61 38 26 39 37 36 35 33 32 31 30 29 41 27 28 85 40 57 58 63 64 65 66 67 68 70 71 42 43 44 49 50 52 53 54 55 56 csel_ h_ce_1 h_ce_2 h_we_ h_ireq_ h_iois16_ h_iord_ h_iowr_ h_wait_ h_inpack_ h_reg_ h_stschg_ dasp_ h_oe_ h_reset h_a(0) h_a(1) h_a(2) h_a(3) h_a(4) h_a(5) h_a(6) h_a(7) h_a(8) h_a(9) h_a(10) h_d(0) h_d(1) h_d(2) h_d(3) h_d(4) h_d(5) h_d(6) h_d(7) h_d(8) h_d(9) h_d(10) h_d(11) h_d(12) h_d(13) h_d(14) h_d(15) _csel -ce1 -ce2 -we -ireq -iois16 -iord -iowr -wait -inpack -reg -stschg -spkr -oe -reset a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 -vs1 -vs2 -cd1 -cd2 xin vcc vcc vcc vcc vcc c0 c1 to 3 xout porst_ 22 23 18 114 99 103 112 113 12 104 105 117 2 3 5 4 101 116 7 6 1 120 119 118 110 109 108 107 100 9 10 11 89 90 91 92 98 13 14 15 93 94 95 97 102 gnd vcc test3 test2 remode test1 45 20 19 120 pin tqfp pc card slot (ata card specification) vcc: 16, 25, 46, 59, 76, 87, 106 gnd: 8, 21, 24, 34, 48, 51, 62, 69, 81, 88, 96, 111 rrceb10 rrceb9 rrceb8 rrceb7 rrceb6 rrceb5 rrceb4 rrceb3 rrceb2 rrceb1 f_da(7) f_da(6) f_da(5) f_da(4) f_da(3) f_da(2) f_da(1) f_da(0) f_cdea_ f_wea_ f_oea_ f_res f_db(7) f_db(6) f_db(5) f_db(4) f_db(3) f_db(2) f_db(1) f_db(0) f_cdeb_ f_web_ f_oeb_ f_res i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 cden wen oen reset i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 cden wen oen reset vcc vss i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 cden wen oen reset i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 cden wen oen reset vcc vss rrst roe vcc gnd 3 1 2, 4 nc nc 4 5 21 vdd vcc vcc cpwr1 cpwr2 out cx0 cx1 ic1 x?al 20mhz reset ic rpwr1 3 vss rpwr2 rxtal vcc cen sc rdy-bsy f_cea_1 f_sc_a1 f_rdy_1 f_cea_3 f_cea_5 f_cea_7 f_cea_9 f_cea_4 f_cea_6 f_cea_8 f_cea_10 f_cea_2 f_sc_a2 f_rdy_2 f_ceb_1 f_sc_b1 f_rdy_1 f_ceb_2 f_sc_b2 f_rdy_2 cen sc rdy-bsy cen sc rdy-bsy cen sc rdy-bsy c4 to 13 ic2 a-1 ic2 a-3 ic2 a-5 ic2 a-7 ic2 a-9 ic2 a-2 ic2 a-4 ic2 a-6 ic2 a-8 ic2 a-10 ic2 b-1 ic2 b-3 ic2 b-5 ic2 b-7 ic2 b-9 ic2 b-2 ic2 b-4 ic2 b-6 ic2 b-8 ic2 b-10 f_ceb_3 f_ceb_5 f_ceb_7 f_ceb_9 f_ceb_4 f_ceb_6 f_ceb_8 f_ceb_10 vcc c14 to 23 rhdd0 to 15
HN29W6484AH03TE-1 71 160m byte (135m byte) (144m byte) (112m byte) 106m byte 80m byte 64m byte 48m byte 32m byte 16m byte 8m byte 48m byte 32m byte 16m byte 8m byte 20 18 16 14 12 10 8 6 4 2 1 6 4 2 1 13, 38 45 39 20 19 18 17 16 15 14 12 11 10 8 21 22 23 2 3 4 5 6 47 48 49 27 28 29 30 31 7 9 36 37 24 32 34 35 41 42 43 44 46 1, 50 26 25 33 40 17, 51 62 56 29 28 27 26 25 24 23 22 12 11 8 30 31 32 2 3 4 5 6 64 65 66 37 38 39 40 41 7 9 15 16 33 42 44 45 58 59 60 61 63 1, 34, 35, 68 36 67 43 57 vcc -spkr -csel a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 -ce1 -oe -we -ireq -iois16 -ce2 -iord -iowr reset -wait -inpack -reg -stschg gnd -cd1 -cd2 -vs1 -vs2 a-1 to a-10, b-1 to b-10 a-1 to a-10, b-1 to b-8 a-1 to a-10, b-1 to b-6 a-1 to a-10, b-1 to b-4 a-1 to a10, b-1 to b-2 a-1 to a-10 a-1 to a-8 a-1 to a-6 a-1 to a-4 a-1 to a-2 a-1 a-1 to a-6 a-1 to a-4 a-1 to a-2 a-1 ata c a r d specification compactflash tm card specification compactflash tm card specification card density used flash memory pieces of flash memory compactflash tm card specification ata card specification signal name (i/o card mode) 615 738 984 861 738 615 984 738 492 246 246 738 492 246 246 number of cylinders 16 8 8 8 8 8 4 4 4 4 2 4 4 4 2 number of heads 32 48 32 32 32 32 32 32 32 32 32 32 32 32 32 number of sectors /track 314,880 283,392 251,904 220,416 188,928 157,440 125,952 94,464 62,976 31,488 15,744 94,464 62,976 31,488 15,744 number of sectors card density for hn29w6411a 20m byte 10m byte 20m byte 10m byte 2 1 2 1 a-1 to a-2 a-1 a-1 to a-2 a-1 ata card specification card density used flash memory pieces of flash memory 320 320 320 320 number of cylinders 4 2 4 2 number of heads 32 32 32 32 number of sectors /track 40,960 20,480 40,960 20,480 number of sectors card density for hn29w8411 sample bill of materials pc card slot pin controller flash memory 20 mhz 100 k w 2 k w 100 k w 1 m w 2 k w 100 k w 100 k w 0 w 1 f 0.1 f 10 pf 1 f 0.1 f ic1 ic2 reset ic x'tal rrst rpwr1 rpwr2 rxtal remode roe rrceb1 to rrceb10 rhdd0 to rhdd15 cpwr1 cpwr2 cx0 to cx1 c0 c1 to c23 specification item
HN29W6484AH03TE-1 72 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
HN29W6484AH03TE-1 73 revision record rev. date contents of modification drawn by approved by 0.0 nov. 27, 1998 initial issue m. shirai t. totsuka 1.0 apr. 16, 1999 correct errors: change of figures for flash memory interface timing and schematic flash card 4. socket and copy register (address 206h) addition of table for drv# 9. status register: addition of description cis information change of address 0a2h, 0cah, 0fch and 12eh change of description for 4. sector count register change of description for 17. set features 81h: enable 8-bit... to disable 8-bit... change of identify drive information: word address 60 to 255 to 62 to 127, 128 to 159 and 160 to 255 addition of description for 23. wear level dc characteristics i sp1 max: tbd to 0.5 ma addition of i sp1 test conditions: cmos level (control signal = v cc C 0.2 v) in memory card mode and i/o card mode dc current waveform change of figures: sector read and sector write addition of figure for power on operation power on reset characteristics change of description and figure attention for card use (notes for host interface design) change of title and description

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